from preprocessing import list_function_inputs, get_oldest_references_from_lambda
from postprocessing import generate_systemverilog
import brahma

# Example Usage


def create_module_from_constrain(constrain):
    inputs = list_function_inputs(constrain)
    def svname(init_name):
        if init_name.find("_") != -1:
            name, offset = init_name.split("_")
            return name + f"_reg[{offset}]"
        else:
            return init_name

    def id2name(ident: int) -> str:
        if ident < len(inputs) - 1: 
            return svname(inputs[ident + 1])
        else :
            return f'v{ident - len(inputs) + 2}'

    synth = brahma.Synthesizer(len(inputs) - 1, constrain)
    res = synth.synthesize_shortest()
    prog = []
    n = 0
    for ident, instr in enumerate(res.instructions):
        if instr.reached :
            n  = ident
            print(ident)
            prog.append(f'    v{ident} = ' + instr.component.expression(*map(id2name, instr.args), res.model))

    prog.append(f"    O = v{ident}")

    return generate_systemverilog(prog, get_oldest_references_from_lambda(constrain))