def generate_systemverilog(
    program_body, 
    inputs,
    module_name="GeneratedModule",
    bit_width=32
):
    """
    Generates a SystemVerilog template with loop-based shift registers and always_comb for logic.

    Args:
        synthesized_program (str): The synthesized program as a lambda function string.
        module_name (str): Name of the generated SystemVerilog module.
        bit_width (int): Bit width for inputs, outputs, and registers.

    Returns:
        str: A SystemVerilog template code as a string.
    """
    # Parse inputs and the body from the synthesized program
    # Example: "lambda I1_1, I1_2: (I1_1 & I1_2) - 1"

    # Generate input declarations
    input_declarations = "\n".join([f"    input logic [{bit_width-1}:0] {base_name};" for base_name in inputs if base_name != "O"])

    # Generate shift register logic using loops
    shift_logic = []
    for base_name, max_offset in inputs.items():
        if max_offset > 0:
            shift_logic.append(f"    logic [{bit_width-1}:0] {base_name}_reg [1:{max_offset}];")
            shift_logic.append(
                f"    always_ff @(posedge clk) begin\n"
                f"        for (int i = {max_offset}; i > 1; i = i - 1) begin\n"
                f"            {base_name}_reg[i] <= {base_name}_reg[i-1];\n"
                f"        end\n"
                f"        {base_name}_reg[1] <= {base_name};\n"
                f"    end"
            )

    # Generate output logic in always_comb
    output_declaration = f"    output logic [{bit_width-1}:0] O;"
    comb_logic = "\n".join(program_body)

    output_logic = f"""
    always_comb begin
{comb_logic}
    end
    """

    # SystemVerilog module template
    sv_template = f"""
module {module_name} (
    input logic clk,
{input_declarations}
{output_declaration}
);

{("\n   ".join(shift_logic))}

{output_logic.strip()}

endmodule
"""
    return sv_template.strip()