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36 lines
1.1 KiB
Python
36 lines
1.1 KiB
Python
from preprocessing import list_function_inputs, get_oldest_references_from_lambda
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from postprocessing import generate_systemverilog
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import brahma
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# Example Usage
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def create_module_from_constrain(constrain):
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inputs = list_function_inputs(constrain)
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def svname(init_name):
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if init_name.find("_") != -1:
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name, offset = init_name.split("_")
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return name + f"_reg[{offset}]"
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else:
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return init_name
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def id2name(ident: int) -> str:
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if ident < len(inputs) - 1:
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return svname(inputs[ident + 1])
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else :
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return f'v{ident - len(inputs) + 2}'
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synth = brahma.Synthesizer(len(inputs) - 1, constrain)
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res = synth.synthesize_shortest()
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prog = []
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n = 0
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for ident, instr in enumerate(res.instructions):
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if instr.reached :
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n = ident
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print(ident)
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prog.append(f' v{ident} = ' + instr.component.expression(*map(id2name, instr.args), res.model))
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prog.append(f" O = v{ident}")
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return generate_systemverilog(prog, get_oldest_references_from_lambda(constrain))
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